1. Field of the Invention
The present invention relates to an electronic camera of the type which has a digital memory.
2. Description of the Related Art
Due to developments in semiconductor memories occurring in recent years, electronic still cameras have been proposed which have a memory for temporarily storing a video signal representative of a single image (a single field or a single frame) obtained by an imaging device. (This signal being stored prior to recording on a disk or the like.) FIG. 1 shows such an electronic still camera.
In this electronic still camera, a light from an object passes through a plurality of optical lenses 1, 2, 3, and 4, a shutter mechanism 5, an infrared radiation cutting filter 6, an optical low-pass filter 7, and an on-chip color filter 8 and reaches the image forming surface of an imaging device 9 which converts the light into an electric signal, as shown in FIG. 1. The obtained video signal is read out to sample-hold circuits 10 separately as R (red), G (green), and B (blue) signals and sampled and held by the sample-hold circuits 10.
The outputs of the sample-hold circuits 10 are gain controlled by variable gain amplifiers 11-1 and 11-2 for controlling white balance and a variable gain amplifier 12 for adjusting the sensitivity, the outputs of the amplifiers 11-1, 12, and 11-2 being respectively supplied to A/D (analog-digital) converters 13-1, 13-2 and 13-3. The A/D converters 13-1, 13-2 and 13-3 have a clamping function and gamma correcting function. Therefore, in addition to A/D conversion, level clamping and gamma correction can also be conducted on the video signal supplied to the A/D converters.
The obtained digital video signal is converted into a switched Y (luminance) signal by a switch 14 which is switched over on a time sharing basis, and then temporarily stored in a normally-used FIFO type memory 15.
The individual components 9 to 14 are operated synchronously with a clock supplied from a clock generating circuit 16 controlled by a system controller 17. The clock generating circuit 16 suspends the supply of the clock signals to the individual components 9 to 14 when the video signal representing a single image has been stored in the memory 15, and thereby reduces power consumption.
The system controller 17 generates a white balance control signal and an iris control signal on the basis of the outputs of an automatic white balance (AWB) sensor 18 and of an automatic iris (AE) sensor 19. The system controller 17 also generates various types of control signals in accordance with the operation of an operation panel 20.
After the video signal representative of a single image has been stored in the memory 15, the stored video signal is read out from the memory 15. The read-out video signal is first supplied to a vertical aperture correcting circuit in sequence.
The vertical aperture correcting circuit includes two series-connected 1H line memories 21-1 and 21-2, and a normally used vertical finite impulse response (FIR) filter 22 composed of coefficient units and an adder. The vertical aperture correcting circuit conducts vertical aperture correction on the video signal supplied thereto. The video signal output from the vertical aperture correcting circuit is converted into an analog signal by a digital-analog (D/A) converter 23. The obtained analog signal passes through a low-pass filter 24 which removes the clock component of the signal, and then a clamping circuit (CL) 25 which clamps the signal to a predetermined level. The video signal further passes through a blanking circuit (BL) 26, then a sink adder 27 which adds a synchronizing signal to the video signal, and is then supplied to a recording/reproducing apparatus 28 which records the video signal on a recording medium, such as a magnetic disk.
The output (the switched Y signal) of the 1H line memory 21-1 of the vertical aperture correcting circuit is separated into color signals of R, G and B by a switch 30. The individual color signals pass through a plurality of horizontal FIR filters 31-1, 31-2 and 31-3, each including a plurality of delay circuits (latch circuits), a plurality of coefficient units and an adder, which limits the band thereof. The resultant color signals are converted into color difference signals by encoders 32 and 33. The obtained color difference signals are supplied to a switch 34 and converted into a line sequential color difference signal.
The resultant line sequential color difference signal is converted into an analog signal by a D/A converter 35. The obtained analog signal passes through a low-pass filter 36, a clamping circuit 37 and a blanking circuit 38 and is then supplied to the recording/reproducing apparatus 28.
The above-described individual components are driven synchronously with a clock supplied from the clock generating circuit 16.
In the thus-arranged electronic still camera, since the 1H line memories 21-1 and 21-2 are required for vertical aperture correction in addition to the memory 15, the scale of the circuit is increased, thus increasing production cost.
Furthermore, the aforementioned digital filters (horizontal FIR filters 31 and vertical FIR filter 22) are large in size and consume a large amount of power. These drawbacks make integration of the digital filters difficult.